1. Field of the Invention
The present invention relates to an LSI verification method and an LSI verification apparatus for verifying a design result of a system-on-chip LSI realizing system functions in hardware and software.
2. Description of the Related Art
A system-on-chip LSI is known in which an entire system specification is divided into a software portion, i.e., a function realized by processing according to a program by a processor in the LSI and a hardware portion, i.e., a function realized by hardware. The software portion and the hardware portion are provided in a one-chip LSI.
In design verification of a system-on-chip LSI, it is necessary to verify equivalence of an entire system specification with a system-on-chip LSI design data, to verify equivalence of a hardware portion with a specification, and to verify matching between the software portion and the hardware portion.
Moreover, in designing a system-on-chip LSI, there is a technique to create a software for generating all the system functions and then the software is divided and converted into a software portion and a hardware portion. The conversion into the hardware portion may be automatically performed by a tool or partially performed manually. This technique is effective for developing a system-on-chip LSI but there is a problem that the automatic conversion of a software operating sequentially into a hardware may fail in realizing a hardware operation intended or conversion mistake may be involved due to the manual operation. Accordingly, verification is indispensable.
For verification of the equivalence, an expected value for an input test pattern is defined in advance according to a design specification, so that a state of an output signal of a simulation result is compared to the expected value.
As such a verification method, for example, Japanese Patent Publication 8-287134 discloses a verification method using a logic circuit performing verification of matching between a software and a hardware.
FIG. 11 shows an outline of a conventional verification method.
In FIG. 11, an architecture simulator 20 has a function for simulating a software portion described in an architecture level. A logic circuit simulator 10 has a function for simulating a hardware portion described in a gate level and additionally contains a control definition 12 defining an execution condition of an architecture simulation as a result of a hardware simulation. In a conventional logic circuit verification method, simulation of the logic circuit is performed according to an input condition and if the logic circuit simulation result satisfies the execution condition of the architecture simulation, the architecture simulation is performed, so that the logic circuit simulation result and the architecture simulation result are compared to the design specification for verification.
In the aforementioned conventional LSI verification method, it is necessary to define an expected value in advance, which complicates the verification. Moreover, since verification is performed by using the logic circuit simulator of the gate level and the architecture simulator of the architecture level, it is impossible to perform verification on a design level other than the gate level and the architecture level. For example, in development of a large-scale LSI, bugs are eliminated as may as possible in the intermediate design phase before proceeding to a next phase, so as to minimize the total development period. However, in the conventional example, verification cannot be performed in an intermediate phase.
Moreover, the conventional example has a problem that verification cannot be performed at a stage when a level other than the gate level and the architecture level is involved. For example, a concurrent design is carried out in development of a large-scale LSI. The design levels are not always matched with one another and there is a possibility that a plurality of design levels are present. In such a state, verification cannot be performed by the conventional example. Furthermore, the logic circuit simulator and the architecture simulator should be interlocked via a control definition. This requires a dedicated logic circuit simulator and a dedicated architecture simulator. Various companies provide various LSI simulator tools. When a user can use a simulation tool the user is accustomed to use or can use a simulation tool of optimal performance available, that is beneficial. However, it is a demerit that a user should select a dedicated simulator.
Moreover, the conventional example has a problem that in order to verify a logic circuit, it is necessary to describe the other portion than the logic circuit at the architecture level and to set a control definition required for this. That is, a work efficiency is low.
It is therefore an object of the present invention to provide an LSI verification method and apparatus appropriate for verification of a system-on-chip LSI.
In order to achieve the aforementioned object, the LSI verification method according to the present invention is for verifying an equivalence between a software for realizing a predetermined function and a hardware data created according to the software so as to constitute a hardware operating identically as a processing by the software, and comprises steps of: simulating each of the hardware data and the software, and comparing a result of simulation by the hardware to a result of simulation by the software.
The LSI verification apparatus according to the present invention is for verifying an equivalence between a software for realizing a predetermined function and a hardware data created according to the software so as to constitute a hardware operating identically as a processing by the software, and comprises:
a recording device for temporarily holding a simulation result; and
a processor for verifying an equivalence by comparing a result of simulation by the hardware data to a result of simulation by the software.
The recording medium according to the present invention contains a program causing a computer to perform verification of an equivalence between a software for realizing a predetermined function and a hardware data created according to the software so as to constitute a hardware operating identically as a processing by the software, wherein
a simulation result is held in a recording device and a result of simulation by the hardware data is compared to a result of simulation by the software for the verification.
Thus, an equivalence between a software and a hardware data operating identically as the software can be verified through comparison of a simulation result of the software with a simulation result of the hardware. Accordingly, there is no need of defining an expected value in advance, which simplifies the verification work.
It should be noted that it is also possible, according to a signal I/O condition defining operation of the hardware, to compare a state of an output signal as a simulation result of the hardware data to a software variable as a simulation result of the software.
As an LSI verification apparatus in this case,
the recording device stores an I/O condition of a signal defining operation of the hardware, and
the processor compares, according the I/O condition, an output signal state as a simulation result by the hardware data to a software variable as a simulation result by the software.
Moreover, in this case, the recording medium contains a program causing a computer to hold the signal I/O condition defining the hardware operation and to compare, according to the I/O condition, an output signal state as a simulation result by the hardware data to a software variable as a simulation result by the software.
Accordingly, the equivalence between a software and a hardware operating identically as the software but having a different operation speed can be verified by comparing a software I/O variable to a corresponding hardware I/O signal. This simplifies the verification work.
Moreover, it is also possible to complete a simulation of the software and then perform a simulation by the hardware while performing the comparison.
In this case, in the LSI verification apparatus, the processor completes a simulation by the software and then performs a simulation by the hardware data while performing the comparison.
In this case, the recording medium contains a program causing a computer to complete a simulation by the software and the perform a simulation by the hardware data while performing the comparison.
Accordingly, it is possible to verify the equivalence while paying attention to the hardware and to easily determine a moment when an NG condition (no good, unacceptable) is caused by the hardware, thus simplifying the verification work.
Furthermore, it is also possible to complete a simulation by the hardware data and then perform a simulation of the software while performing the comparison.
In this case, in the LSI verification apparatus, the processor completes a simulation by the hardware and then performs a simulation by the software while performing the comparison.
In this case, the recording medium contains a program causing a computer to complete a simulation by the hardware data and then perform a simulation by the software while performing the comparison.
Accordingly, it is possible to perform verification while paying attention to the software and to easily determine a moment when an NG condition (no good, unacceptable) is caused by the software processing, thus simplifying the verification work.